Verilog code coverage analysis tool
DescriptionCovered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
149 other people were interested in this package here. The newest known version of this software is 0.7.10-3 (Information last updated about 7 hours ago.)
Upload new screenshots
Thanks for uploading more screenshots. Please note:
- Your screenshot should contain a typical scene when working with it.
- Take only a screenshot of the respective application and not of your whole desktop (unless the screenshot is meant for a window manager).
- Your screenshots must be in PNG format.
- You can upload multiple images at once.
- Your screenshot need to be approved by the moderators first. You will already see your screenshot but it will not be visible to others instantly. If moderators reject your upload you will get notified next time you visit this site (requires cookies).
- Images larger than 800x600 pixels will automatically be reduced. So don't try to capture too much detail in a screenshot. It may become unreadable. Shrink the applications window if possible.
- Screenshots are made public and can freely be used by anyone.
- Useful programs for making screenshots are shutter, ksnapshot (KDE), gimp, xwd or scrot. See the Debian wiki for more information on how to make screenshots under Debian.
- Please set your language to english so that everybody understands it. If you don't use english by default please start your application from a shell using after setting "export LANG=C".