Verilog code coverage analysis tool
DescriptionCovered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
588 other people were interested in this package here. The newest known version of this software is 0.7.10-3+b1 (Information last updated about 16 hours ago.)
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