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Verilog simulator


Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.


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35 other people were interested in this package here. The newest known version of this software is 2.12a-1.1 (Information last updated about 23 hours ago.)