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iverilog

Icarus verilog compiler

Description

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

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Homepage

http://iverilog.icarus.com


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931 other people were interested in this package here. The newest known version of this software is 10.1-0.1+b1 (Information last updated about 9 hours ago.)