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Icarus verilog compiler


Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

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4814 other people were interested in this package here. The newest known version of this software is 10.1-0.1+b2 (Information last updated about 22 hours ago.)