Open on-chip JTAG/SWD debug solution for embedded target devices
DescriptionOpenOCD aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. The debugger uses an IEEE 1149-1 compliant JTAG TAP bus master to access on-chip debug functionality available on ARM based microcontrollers or system-on-chip solutions. For MIPS systems the EJTAG interface is supported. Additionally there is support for eSi-RISC, Intel, OpenRISC, RISC-V and ARC controllers. User interaction is realized through a telnet command line interface, a gdb (the GNU debugger) remote protocol server, and a simplified RPC connection that can be used to interface with OpenOCD's Jim Tcl engine. OpenOCD supports many different types of JTAG interfaces/programmers.
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