Gate-level Static Timing Analyzer
DescriptionAfter synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs. It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
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Install this software package
If the package is available for the distribution you are currently using on your computer then install the software by clicking on…Install opensta