opensta
Gate-level Static Timing Analyzer
Description
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs. It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.Upload more screenshots
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Homepage
https://github.com/The-OpenROAD-Project/OpenSTA
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