fast free Verilog simulator
DescriptionVerilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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Install this software package
If the package is available for the distribution you are currently using on your computer then install the software by clicking on…Install verilator