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verilog

Icarus verilog compiler (transitional package)

Icarus verilog compiler (transitional package)
from version 0.9.7-1

Description

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

Homepage

http://iverilog.icarus.com


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