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Icarus verilog compiler (transitional package)

Icarus verilog compiler (transitional package)
from version 0.9.7-1


Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

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3203 other people were interested in this package here. The newest known version of this software is 10.1-0.1 (Information last updated about 9 hours ago.)