Framework for Verilog RTL synthesis
DescriptionThis is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
3141 other people were interested in this package here. The newest known version of this software is 0.9-1 (Information last updated about 8 hours ago.)
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