yosys-abc

Sequential Logic Synthesis and Verification Algorithms

Description

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

Upload more screenshots

Please help extend the collection of screenshots. Just make a screenshot and upload it here. You don't need to register or anything.

Upload a screenshot

Hint: upload an image here from your clipboard with Ctrl-V


Homepage

https://github.com/YosysHQ/yosys


Install this software package

If the package is available for the distribution you are currently using on your computer then install the software by clicking on…

Install yosys-abc