yosys-plugin-ghdl
VHDL to RTL synthesis plugin using GHDL
Description
This yosys plugin allows running RTL synthesis from VHDL source code instead of yosys' native Verilog. This allows a full synthesis flow from VHDL to hardware for FPGAs where the GHDL compiler is used to analyse the VHDL sources and yosys is used to perform logic optimization, technology mapping and convertion to netlist format.Upload more screenshots
Please help extend the collection of screenshots. Just make a screenshot and upload it here. You don't need to register or anything.
Upload a screenshotHint: upload an image here from your clipboard with Ctrl-V
Homepage
https://github.com/ghdl/ghdl-yosys-plugin
Install this software package
If the package is available for the distribution you are currently using on your computer then install the software by clicking on…
Install yosys-plugin-ghdl