VHDL to RTL synthesis plugin using GHDL


This yosys plugin allows running RTL synthesis from VHDL source code instead of yosys' native Verilog.

This allows a full synthesis flow from VHDL to hardware for FPGAs where the GHDL compiler is used to analyse the VHDL sources and yosys is used to perform logic optimization, technology mapping and convertion to netlist format.

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Install this software package

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Install yosys-plugin-ghdl