sugar-pippy-activity
Sugar Learning Platform - Python programming activity
Sugar Learning Platform promotes collaborative learning through Sugar
Activities that encourage critical thinking, the heart of a quality
education. Designed from the ground up especially for children, Sugar
offers an alternative to traditional “office-desktop” software.
tenace
Bridge hand viewer and editor
Tenace is a Bridge hand viewer and editor. Hand records are read using
BBO's .lin format. The board editor allows one to easily move cards around to
simulate different distributions. The double dummy solver computes optimal
lines of play and par scores.
texlive-latex-recommended
TeX Live: LaTeX recommended packages
A collection of recommended add-on packages for LaTeX which have widespread
use.
tilda
GTK+ based drop down terminal for Linux and Unix
Tilda is a terminal emulator similar to normal terminals like
gnome-terminal (GNOME) or Konsole (KDE), with the difference
that it drops down from the edge of a screen when a certain configurable
hotkey is pressed. This is similar to the build-in consoles in
games such as Quake or Half-live. Tilda is highly configureable
through a graphical wizard.
tkabber-plugins
standard plugins for Tkabber, an XMPP (Jabber) client
This package provides the set of standard plugins for Tkabber,
a sophisticated XMPP (Jabber) GUI client.
These plugins provide various functional enhancements for Tkabber,
implement several board games for two players and much more.
tkgate
Tcl/Tk based digital circuit editor and simulator
TkGate is a digital circuit editor and simulator with a Tcl/Tk based
interface. TkGate includes a large number of built-in devices including basic
gates, memories, ttys and modules for hierarchical design. The simulator can
be controlled either interactively or through a simulation script. Memory
contents can be loaded from files, and a microcode/macrocode compiler (gmac)
is included to create tkgate memory files from a high-level description. The
simulator supports continuous simulation, single step simulation (by clock or
epoch) and breakpoints. Save files are in a Verilog-like format.