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framework providing Verilog support


Verilog is a Perl framework providing Verilog support in the Perl language. It includes:

 * Verilog::Getopt, which parses command line options similar to C++ and VCS
 * Verilog::Language, which knows the language keywords and parses numbers.
 * Verilog::Netlist, which builds netlists out of Verilog files. This allows
   easy scripts to determine things such as the hierarchy of modules.
 * Verilog::Parser, which invokes callbacks for language tokens
 * Verilog::Preproc, preprocesses the language, and allows reading
   post-processed files right from Perl without temporary files.

It also includes a variety of useful utilities:

 * vpassert inserts PLIish warnings and assertions for any simulator
 * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog
 * vrename renames and cross-references Verilog symbols. It creates Verilog
   cross references and makes it easy to rename signal and module names over
   multiple files.

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