alien-hunter
Interpolated Variable Order Motifs to identify horizontally acquired DNA
Alien_hunter is an application for the prediction of putative
Horizontal Gene Transfer (HGT) events with the implementation of
Interpolated Variable Order Motifs (IVOMs). An IVOM approach
exploits compositional biases using variable order motif distributions
and captures more reliably the local composition of a sequence compared
to fixed-order methods. Optionally the predictions can be parsed into a
2-state 2nd order Hidden Markov Model (HMM), in a change-point detection
framework, to optimize the localization of the boundaries of the
predicted regions. The predictions (embl format) can be automatically
loaded into Artemis genome viewer freely available at:
http://www.sanger.ac.uk/Software/Artemis/.
ucarp
user-space replacement to VRRP automatic IP fail-over
UCARP allows a pair of hosts to share common virtual IP addresses in
order to provide automatic fail-over. It is a portable user-land
implementation of the secure and patent-free Common Address Redundancy
Protocol (CARP, OpenBSD's alternative to the VRRP).
gccgo-multilib-s390x-linux-gnu
Go compiler (based on GCC) for the s390x architecture
This is the GNU Go compiler, which compiles Go on platforms supported by
the gcc compiler. It uses the gcc backend to generate optimized code.
python-async
framework to process interdependent tasks in a pool of workers
Async is one more attempt to make the definition and execution of
asynchronous interdependent operations easy. For that to work, you may
define tasks which communicate with each other by channels. Channels
transfer items, which is very similar to bytes flowing through pipes
uses in inter-process communication. Items will only be generated on
demand, that is when you read from the respective output channel.
python-migrate
Database schema migration for SQLAlchemy - Python 2.7
Inspired by Ruby on Rails' migrations, migrate provides a way to deal
with database schema changes in SQLAlchemy projects.
covered
Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and
a generated VCD/LXT dumpfile from that design and generates a coverage file
that can be merged with other coverage files or used to create a coverage
report. Covered also contains the GUI coverage report utility that reads in a
coverage file to allow interactive coverage discovery. Areas of coverage
measured by Covered are: line, toggle, memory, combinational logic, FSM
state/state-transition and assertion coverage.